As the complexity of integrated circuits increases, it becomes more and more important to achieve very high fault coverage while minimizing test cost. Although traditional scan-based methods have been quite successful in meeting these goals for sub-million gate designs during the past few decades, for recent scan-based designs larger than one-million gates, achieving this very high fault coverage at a reasonable price has become quite difficult. This is mainly due to the fact that it requires a significant amount of test-data storage volume to store scan patterns onto the automatic test equipment (ATE). In addition, this increase in test-data storage volume has resulted in a corresponding increase in the costs related to test-application time.
Conventional approaches for solving this problem focus on either adding more memory onto the ATE or truncating part of the scan data patterns. These approaches fail to adequately solve the problem, since the former approach adds additional test cost so as not to compromise the circuit's fault coverage, while the latter sacrifices the circuit's fault coverage to save test cost.
As an attempt to solve this problem, a number of prior art design-for-test (DFT) techniques have been proposed. These solutions focus on increasing the number of internal scan chains, in order to reduce test-data volume and hence test application time without increasing, and in some cases while decreasing or eliminating the number of scan-chains that are externally accessible. This removes package limitations on the number of internal scan chains that in some cases can even exceed the package pin count.
An example of such a DFT technique is Built-In Self-Test (BIST). See U.S. Pat. No. 4,503,537 issued to McAnney (1985). BIST implements on-chip generation and application of pseudorandom scan patterns to the circuit under test eliminating all external access to the scan-chains, and hence removing any limitation on the number of internal scan-chains that can be used. BIST, however, does not guarantee very high fault coverage and must often be used together with scan ATPG (automatic test pattern generation) to cover any remaining hard-to-detect faults.
Several different approaches for compressing test data before transmitting them to a circuit under test have been proposed. See the papers co-authored by Koenemann et al. (1991), Hellebrand et al. (1995), Rajski et al. (1998), Jas et al. (2000), Bayraktaroglu et al. (2001), and U.S. Pat. No. 6,327,687 issued to Rajski et al. (2001). These methods are based on the observation that test cubes (i.e., arrangements of scan data patterns stored within the scan chains of a circuit under test) often contain a large number of unspecified (don't care) positions. It is possible to encode such test cubes with a smaller number of bits and later decompress them on-chip using an LFSR (linear-feedback shift register) based decompression scheme. This scheme requires solving a set of linear equations every time a test cube is generated using scan ATPG. Since solving these linear equations depends on the number of unspecified bits within a test cube, these LFSR-based decompression schemes often have trouble compressing an ATPG pattern without having to break it up into several individual patterns before compression, and hence have trouble guaranteeing very high fault coverage without having to add too many additional scan patterns.
A different DFT technique to reduce test data volume is based on broadcast scan. See the papers co-authored by Lee (1999) et al., Hamzaoglu et al. (1999), and Pandey et al. (2002). Broadcast scan schemes either directly connect multiple scan chains, called broadcast channels, to a single scan input or divide scan chains into different partitions and shift the same pattern into each partition through a single scan input. In these schemes, the connections between each and every scan input and its respective broadcast channels is done using either wires or buffers, without any logic gates, such as AND, OR, NAND, NOR, XOR, XNOR, MUX (multiplexer), or NOT (inverter) in between. Although it is possible to implement this scheme with practically no additional hardware overhead, it results in scan chains with very large correlation between different scan-chain data bits, resulting in input constraints that are too strong to achieve very high fault coverage.
Accordingly, there is a need to develop an improved method and apparatus for guaranteeing very high fault coverage while minimizing test data volume and test application time. The method we propose in this invention is based on broadcast scan, and thus, there is no need to solve any linear equations as a separate step after scan ATPG. A broadcast scan reordering approach is also proposed to further improve the circuit's fault coverage.
Test power issue is becoming a major challenge as scan-based designs reach multi-million gates. Power dissipation during scan testing is much higher than during normal circuit operation. It is important to reduce test power dissipation during scan testing since the circuit under test can be damaged by excessive heat. Various approaches have been proposed to alleviate the test power problem, often at the cost of higher test application time. In the paper co-authored by Wang, et al., an automatic test pattern generation ATPG based (ATPG-based) method was proposed. In the paper co-authored by Kajihara et al., a method to reduce test power using vector modification was described. A double-tree scan architecture for power reduction was proposed in the paper co-authored by Bhattacharya et al. The co-authors Wen et al. discussed a method to reduce capture power during scan testing. All these methods target scan-based designs where the storage elements are converted into scan cells, like multiplexed-D flip-flops or LSSD SRLs (shift register latches).
To solve the test power problem without adding much test application time, a random access scan (RAS) architecture authored by Ando can be used as opposed to the conventional serial scan architecture in a scan-based design. Each random access scan cell in the RAS architecture is randomly and uniquely addressable in the random access manner. Two new RAS architectures aiming to reduce the silicon overhead were proposed in the papers co-authored by Baik et al. and Mudlapur et al. However, all these methods can only achieve a reduction of test data volume and test application time by around 2 times (2×), although test power can be reduced by 100×.